In the past few years, researchers have investigated various approaches to fabricating FETs which range from using carbon nanotube to using graphene devices, nanowire Si and SiGe FETs, and Ge and InGaAs FETs. Unfortunately however, current FETs have only one inversion layer which is formed in the proximity of the gate insulator. Accordingly, this limits the current FETs to only exhibit two states: ON and OFF. Thus, the applications for current transistors are limited in that designs must take into account the bi-state functionality of the FETs. Accordingly, functionality of current FETs are limited.
One such example is seen in FIG. 1a which illustrates a single channel FET in accordance with the prior art. Another such example is seen in FIG. 1b which illustrates a floating gate memory cell having an asymmetric source/drain, with the drain side of p-type halo or pocket doping in accordance with the prior art. Still yet another example is shown in FIG. 1c which illustrates a NOR array architecture of a floating gate memory cell and which shows erasing in accordance with the prior art. Still yet another example is shown in FIG. 1d which illustrates a NAND array architecture of a floating gate memory cell in accordance with the prior art. Furthermore, other examples are shown in FIG. 2a which illustrates a quantum dot gate 3-state FET and FIG. 2b which illustrates a conventional nanocrystal quantum dot floating gate memory both in accordance with the prior art. It should be appreciated that although the quantum dot gate FET of FIG. 2a does exhibit 3-states, the intermediate state (i.e. the third state) is a low-current state near the threshold region, which is undesirable.